Once formation of semiconductor devices and interconnect structures on a semiconductor wafer (substrate) is completed, the semiconductor wafer is diced into semiconductor chips, or “dies.” Functional semiconductor chips are then packaged to facilitate mounting on a circuit board. A package is a supporting element for the semiconductor chip that provides mechanical protection and electrical connection to an upper level assembly system such as the circuit board. Two types of packaging technologies are commonly available. The first type is wire bonding that employs bonding pads and solder bumps on the semiconductor chip and on a wirebond package. Bonding wires connect pairs of bonding pads across the semiconductor chip and the wirebond package to provide electrical connection between them. The second type is Controlled Collapse Chip Connection (C4) packaging, which employs C4 balls each of which contacts a C4 pad on the semiconductor chip and another C4 pad on a packaging substrate. Both types of packaging technologies provide a packaged semiconductor chip which may be assembled on the circuit board.
Typically, a semiconductor chip having a large number of input/output (I/O) pins employs C4 packaging since C4 packaging can handle a higher density of pins than wire bonding packages. FIG. 1 shows a prior art packaging substrate comprising a core 3 at the center, multiple vertically stacked front metal interconnect layers 5 located above the core 3, multiple front insulator layers 4 interspersed between the front metal interconnect layers 5 and above the core 3, multiple vertically stacked backside metal interconnect layers 7, and multiple back insulator layers 6 interspersed between the backside metal interconnect layers 7. Each of the front insulator layers 4 provides electrical isolation between a pair of neighboring front metal interconnect layers 5. Likewise, each of the back insulator layers 6 provides electrical isolation between a pair of neighboring backside metal interconnect layers 7. Typically, the number of front metal interconnect layers 5 matches the number of the backside metal interconnect layers 7. Recent activity with organic laminates has been to eliminate the core. The presence or lack of a core does not change how this invention works.
The packaging substrate facilitates formation of an electrical link between the semiconductor chip and a system board of a computer. A semiconductor chip is mounted on a die foot print area 2 located on a top surface of the packaging substrate. The die foot print area 2 contains C4 pads on which a semiconductor chip (not shown) may be attached by C4 bonding. The area of the top surface of the packaging substrate outside of the die foot print area 2 is referred to as a packaging substrate top surface 1.
A typical semiconductor chip employing a packaging substrate may comprise about 5,000 input/output nodes. Each of these nodes are electrically connected to a C4 pad on a top surface of the semiconductor chip in a two dimensional array. Typical two dimensional array configurations for the C4 pads include 4 on 8 configuration, which employs C4 solder balls having a diameter of 4 mils (˜100 microns) and a pitch of 8 mils (˜200 microns) in a rectangular array, and 3 on 6 configuration, which employs C4 solder balls having a diameter of 3 mils (˜75 microns) and a pitch of 6 mils (˜150 microns) in a rectangular array. Thus, more than 5,000 C4 solder balls may be formed on the semiconductor chip, which may be typically about 2 cm×2 cm in size.
The front metal interconnect layers 5 and the backside metal interconnect layers 7 provide electrical connections from the C4 pads on the die foot print area 2 to the bottom of the packaging substrate which contains ball grid array (BGA) pads having a larger dimension than the C4 pads. Typically, BGA pads are in a rectangular array having a pitch on the order of about 1 mm. BGA solder balls having a diameter of about 400 microns are used to attach the packaging substrate to the system board. Typically, Sn—Ag—Cu alloys, which are free of lead, are employed to meet emerging standards for reducing hazardous materials. Alternative methods to BGA connection are to employ a land grid array (LGA) in which a thin pad containing metal points in a grid are placed between the system board and the packaging substrate or to utilize pins. Use of the LGA or pins facilitates easy removal of a packaging substrate containing expensive electronics for repair purposes.
The packaging substrate also protects the semiconductor chip that is mounted on the die foot print area 2 and modularizes the product development of the semiconductor chip, while simplifying the subsequent integration steps involved in the manufacturing of a larger computer or a consumer electronic product. Ceramic materials or organic materials may be employed for building up a packaging substrate. Ceramic substrates are built layer by layer without the need of a core where as organic substrates require a core on which the front and back layers can be built. While ceramic materials offer excellent mechanical strength and a low level of warp relative to organic materials, there is an inherent limitation in wiring density posed by ceramic substrate. It necessarily requires a larger number of buildup layers (by a factor of 5 to 10) than that required by an organic substrate In contrast, an organic substrate facilitates high density wiring in the front metal interconnect layers 5 and the backside metal interconnect layers 7, i.e., a packaging substrate employing an organic material for the core 3, the top insulator layers 4, and the bottom insulator layers 6. Typically, approximately 16 levels of the front metal interconnect layers 5 and the backside metal interconnect layers 7 may accommodate the contents of the electrical wiring in 100 levels in a ceramic package.
The C4 pads on the die foot print area 2 accommodate C4 balls that provide electrical connection to the semiconductor chip. High current through the C4 balls during the operation of the semiconductor chip, however, raises reliability issues of the C4 pads formed on the packaging substrate. In this regard, a key reliability concern is susceptibility of the C4 balls and C4 pads to electromigration. Electromigration is the transport of material caused by the gradual movement of the metal ions in a metallic conductor due to the momentum transfer by electrons conducting electrical current. In time, electromigration may cause an open between a C4 pad and a C4 ball.
When Cu of a C4 pad and Sn of a C4 ball are in direct contact, as is the case in prior art C4 structures, Cu is available to readily diffuse into the C4 ball, which comprises a Sn based solder, during thermal cycles which leaves behind Kirkendall voids, which are voids induced by diffusion in an alloy of two metals that have different interdiffusion coefficients. These Kirkendall voids enhance the transport of Cu. This further increases probability of interfacial void formation at the interface between the C4 pad and the C4 ball. Thus, the rate of Cu transport into the solder accelerates once voids form, and may cause a reliability failure of the electrical connection between the semiconductor chip and the packaging substrate.
The composition of metallic layers employed in the C4 pads to attach a C4 ball is called an “underbump metallurgy” or a “UBM” in the art. In view of the above, there exists a need for an underbump metallurgy that provides enhanced reliability of C4 bonding structures between a semiconductor chip and a packaging substrate.
The industry has used and continues to use a “UBM” of electroless NiP/Au. This “UBM” does not require electrical connection to deposit. However, it has three significant drawbacks. The first is that the deposit needs to be made homogenous after plating. This is done with a furnace step and adds additional processing requirements. The second is that due to the ability of the bath to plate on many surfaces, the bath must be maintained within tight process controls. This requires heavy maintenance of the bath and eventual dumping. The third is that upon interaction with the solder, the Ni will react but the P will not. This leads to the phenomenon known as “black pad”. This “black pad” is brittle and can lead to mechanical failure that causes an electrical open to form.
In view of the above, there exists a need for underbump metallurgy for a packaging substrate for reducing electromigration between a C4 pad and a C4 ball and structures and methods for implementing the same.